1. Field of the Invention
The present invention relates to a semiconductor device, and in particular to a multi-port static random access memory (hereinafter, referred to as “SRAM”) having a high operation speed. Further, the present invention relates to SRAM in which an occupation area of memory cells laid out on a substrate can be reduced by the formation of an electrical connection layer only within first unit cell in arrangement of memory cell array, for providing a common power supply source to the arrangement of memory cell array.
2. Description of the Related Art
In a conventional SRAM, every first unit cell has a flip-flop circuit including a pair of access transistors, a pair of drive transistors, and a pair of load transistors. Compared to first unit cell having a resistor as a load device in the conventional SRAM first unit cell having a bulk-type PMOS transistor as a load transistor has a lower stand-by current and is good in view of memory cell stability. Moreover, it has widely been used as an embedded memory cell in a conventional SRAM since first unit cell having a resistor as a load device and first unit cell having a bulk-type PMOS transistor as a load transistor had the same steps of a production process. Therefore, a multi-port SRAM has been developed for the purpose of increasing the operation speed of its data input/output and of having a wide system application from such a conventional SRAM. In such a multi-port SRAM, increasing the number of transistors in first unit cell is bad in view of an integration density. Problems such as an integration density, a process margin, and a reliability of an operation speed, however, now do not matter owing to the development of a production process art. A wide system application can be enough to load on people's attentions.
FIG. 1 is a circuit configuration diagram of first embodiment according to a conventional two-port SRAM.
In FIG. 1, a load transistor for common use, a drive transistor for carrying out a write operation, and an access transistor for carrying-out a read operation are shown in first unit cell. There are a pair of read bit line RB and /RBB and a pair of write bit line WB and /WBB in a vertical direction. There are a power supply voltage VCC and a write word line WWL in the upper part of first unit cell, and a power supply ground VSS and a read word line RWL in the lower part of first unit cell.
As be shown in FIG. 1, a pair of write access transistors WTA1 and WTA2, and a pair of read access transistors RTA1 and RTA2, a pair of load transistors TL1 and TL2, a pair of write drive transistors WTD1 and WTD2, and a pair of read drive transistors RTD1, and RTD2 consist of first unit cell. All the above described transistors have a set of first and second electrodes and gate electrode. Gate electrodes of the write access transistors WTA1 and WTA2 in first unit cell are respectively and electrically connected to a write word line WWL. Each of first electrodes of the write access transistors WTA1 and WTA2 is electrically coupled to the corresponding bit line of the pair of write bit line WB and /WBB. Also, gate electrodes of the read access transistors RTA1 and RTA2 are respectively and electrically connected to the read word line RWL. Each of first electrodes of the read access transistors RTA1 and RTA2 is electrically coupled to the corresponding read bit line of the pair of read bit lines RB and /RBB. Each of first electrodes of the load transistors TL1 and TL2 is respectively connected to power supply voltage VCC. Each of gate electrodes of the load transistors TL1 and TL2 is respectively connected to a first pair of common nodes CN1 and CN2. First common node CN1 is electrically linked to second common node CN2 in the first pair of common nodes CN1 and CN2. First write drive transistor WTD1 at the pair of write drive transistors WTD1 and WTD2 and first read drive transistor RTD1 at the pair of read drive transistors RTD1 and RTD2 are in series connected to first load transistor TL1 at the pair of load transistors TL1 and TL2. Each of gate electrodes of first write drive transistor WTD1 and first read drive transistor RTD1 is respectively connected to second common node CN2 of the first pair of the common nodes CN1 and CN2. A serial connection of second write drive transistor WTD2 and second read drive transistor RTD2 is linked to second load transistor TL2. And each of gate electrodes of second write drive transistor WTD2 and second read drive transistor RTD2 is commonly connected to the first pair of common nodes CN1 and CN2. Second electrodes of first load transistor TL1 and first write access transistor WTA1 and first electrode of first write drive transistor WTD1 are electrically linked to each second through first common node CN1.
Further, second electrodes of second load transistor TL2 and second write access transistor WTA2 and first electrode of second write drive transistor WTD2 are mutually connected to second common node CNB, too. Second electrode of first write drive transistor WTD1 and first electrode of first read drive transistor RTD1 are respectively connected to the power supply ground VSS. Each of second electrodes of the pair of read access transistors RTA1 and RTA2 which are PMOS transistors, is respectively connected to the corresponding electrode of the pair of read drive transistors RTD1 and RTD2. And write access transistors WTA1 and WTA2, read access transistors RTA1 and RTA2, write drive transistors WTD1 and WTD2, read drive transistors RTD1 and RTD2 are NMOS transistors. First electrode of first load transistor TL1 is electrically connected to power supply voltage VCC, together with second load transistor TL2 included in the second unit cell neighbored to the corresponding first unit cell. Also, an electrical common connection of first electrode of second load transistor TL2 and first load transistor included in second unit cell neighbored to the corresponding first unit cell is made via power supply voltage VCC. First write drive transistor WTD1 and first read drive transistor RTD1 transistor included in first unit cell are electrically linked to power supply ground VSS, together with second write drive transistor and second read drive transistor neighbored to the corresponding first unit cell. Second write drive transistor WTD2 and second read drive transistor RTD2 are electrically coupled to power supply ground VSS, together with write drive transistor and read drive transistor included in second unit cell neighbored to the corresponding first unit cell.
FIG. 2a to FIG. 2i are patterned layout configuration diagrams for explaining process steps of first embodiment of a two-port SRAM according to a prior art invention.
In FIG. 2a, an N-type well region 22 is formed on first part of a cell formation region 21 in order to define a PMOS transistor which is used as a load transistor, wherein the cell formation region 21 is not a fixed region, rather than can be varied. Second region except the N-type well region 22 in the cell formation region 21 is a P type well region. By a formation of a device isolation layer (not shown) in a field region 23 of the cell formation region 21 are made first to seventh active regions 24a to 24g as shown in FIG. 2b. In FIG. 2c, first to fourth electrode patterned layers 25a to 25d are passed through over at least any first portion of the first to seventh active regions 24a to 24g. By exposing the first to seventh active regions 24a to 24g using the first to fourth electrode patterned layers 25a to 25d impurity regions (not shown) are formed within the substrate surfaces of their regions 24a to 24g. A selective exposure of the impurity regions or the first to seventh active regions 24a to 24g makes a formation of a plurality of contact regions 26 which are selectively etched after repeatedly carrying out a formation of an insulation layer between first layer and a corresponding second layer over contact regions 26 in FIG. 2d. 
As shown in FIG. 3a, an N-type well region 22 is formed in order to function as a pair of first and second load transistors TL1 and TL2. A formation of first and second active regions 24a and 24b is made by a separation of the N-type well region 22 to horizontal direction. In some region except N type well region 22 in the cell formation region 21 which is a P-type well region, third and fourth active regions 24c and 24d which face each second are formed by meeting at least first extension portion to a perpendicular direction from an intersection between a long axis of a horizontal direction and a long axis of a vertical direction. Also, fifth active region 24e is formed on a separation region of first and second active regions 24a and 24b. Sixth and seventh active regions 24f and 24g are respectively formed on left and right lower portions of third and fourth active regions 24c and 24d. A first metal electrode layer 25a is formed in order to be utilized as gate electrodes of first load transistor TL1, first write drive transistor WTD1, and first read drive transistor RTD1. First metal electrode layer 25a has a configuration in which a central portion of first active region 24a is passed on in a vertical direction and at least two portions of third active regions 24c are passed on. Second metal electrode layer 25a is formed so that a central portion of second active regions 24d are passed on. As gate electrodes of second load transistor TL2, second write drive transistor WTD2, and second read drive transistor RTD2 functions first metal electrode layer 25a. Third metal electrode layer 25c is formed in order to be utilized as gate electrodes of first and second write access transistors WTA1 and WTA2. Third metal electrode layer 25c has a configuration in which third and fourth active regions 24c and 24d are respectively passed on to vertical direction and their vertical extension portions are met at a predetermined position with each second so that a horizontal extension portion is formed in a horizontal direction. Fourth metal electrode layer 25d which is utilized as gate electrodes of first and second read access transistor RTA1 and RTA2, is formed so that the lower portions of third and fourth active regions 24c and 24d are passed on at the same time. Further, a plurality of contact regions 26 are formed on first to seventh active regions 24a to 24g of which any portion are not passed on by first to fourth first to fourth metal electrode layer 25a to 25d or on first to fourth metal electrode layer 25a to 25d. Fifth active region 24e is formed in order to be defined as well bias of N type well region 22. After carrying out a process step for the purpose of obtaining the above described patterned configuration, a process step for forming a first group of metal electrical wires including metal electrical wire layers 27a to 27m is performed as shown in FIG. 2e. 
In FIG. 2e, first to fifth metal electrical wire layers 27a to 27e are formed in order to be utilized as a power supply voltage VCC, a write word line WWL, a read word line RWL, etc., and sixth to thirteenth metal electrical wire layers 27f to 27e are formed in order to be utilized as an interior electrical wire. A plurality of via holes 28 are formed, as shown in FIG. 2f, on first to thirteenth metal electrical wire layers 27a to 27e. In FIG. 3b, first metal electrical wire layer 27a is electrically contacted with first electrodes of first and second load transistors TL1 and TL2. A electrical connection of gate electrodes of first load transistor TL1, first write drive transistor WTD1, and read drive transistor RTD1, and first common node CN1 is made by second metal electrical wire layer 27b. Third metal electrical wire layer 27c causes second common node CN2 to make an electrical connection of gate electrodes of second load transistor TL2, second write drive transistor WTD2, and second read drive transistor RTD2. Fourth metal electrical wire layer 27d which is a horizontal extension, is formed in order to electrically contact with gate electrodes of first and second write access transistor WTA1 and WTA2. In order to electrically contact with gate electrodes of first and second read access transistors RTA1 and RTA2, fifth metal electrical wire layer 27e is formed. Sixth and seventh metal electrical wire layer 27f and 27g are formed in order to electrically contact with first electrodes of first and second write access transistors WTA1 and WTA2. Eighth and ninth metal electrical wire layers 27h and 27i are formed in order to be electrically contacted with first electrodes of first and second read access transistors RTA1 and RTA2. With third common node CN3 of first write drive transistor WTD1 and first read drive transistor RTD1 is electrically contacted tenth metal electrical wire layer 27j. Eleventh metal electrical wire layer 27k is formed in order to electrically contact with fourth common node CN4 of second write drive transistor WTD2 and second read drive transistor RTD2. Twelfth and thirteenth metal electrical wire layers 27l and 27m are formed in order to contact with power supply voltage VCC. First plurality of via holes are respectively formed on sixth to thirteenth metal electrical wire layer 27f to 27m. After carrying out process step for the purpose of obtaining the patterned configuration as shown in FIG. 2e, process step for forming a second group of metal electrical wires including metal electrical wire layers 29a to 29f is performed as shown in FIG. 2g. 
In FIG. 2g, first metal electrical wire layer 29a and second metal electrical wire layer 29b are formed so that these metal electrical wire layers 29a and 29b may pass on edge parts of both left and right portions of a cell formation region 21 to a vertical direction. First metal electrical wire layer 29a and second metal electrical wire layer 29b function as power supply ground VSS. Third and fourth metal electrical wire layers 29c and 29d are formed in order to function as a pair of read bit line RB and /RBB. Also, third and fourth metal electrical wire layers 29e and 29f are separated from each second at a predetermined distance between first and second metal electrical wire layers 29a and 29b so that these metal electrical wire layers 29c and 29d may face. Fifth and sixth metal electrical wire layers 29e and 29f are formed, for the purpose of functioning as a pair of write bit lines WB and /WBB, so that third and fourth metal electrical wire layers 29c and 29d are separated from each second at a predetermined distance between third and fourth metal electrical wire layers 29c and 29d with a shape of an inverse face of these metal electrical wire layers 29e and 29f On any end of first and second metal electrical wire layers are second plurality of via holes 30, for the purpose of contacting with power supply ground VSS as known in FIG. 2f. Further, a third group of metal electrical wires including metal electrical wire layers 31a to 31c are formed in a horizontal direction as known in FIG. 2g. 
In FIG. 3c, tenth electrical wire layer 27j and twelfth electrical wire layer 27l of the first metal electrical wire group are electrically coupled through first via holes to first electrical wire layer 29a of the second metal electrical wire group. Eleventh electrical wire layer 27k and thirteenth electrical wire layer 27m of the first metal electrical wire group are electrically contacted through first via holes with second electrical wire layer 29b of the second metal electrical wire group. Eighth electrical wire layer 27h of the first metal electrical wire group are electrically contacted through first via holes with third electrical wire layer 29c of the second metal electrical wire group. Ninth electrical wire layer 27i of the first metal electrical wire group are electrically contacted through first via holes with fourth electrical wire layer 29d of the second metal electrical wire group. Sixth electrical wire layer 27f of the first metal electrical wire group are electrically contacted through first via holes with fifth electrical wire layer 29e of the second metal electrical wire group. Seventh metal electrical wire layer 27g of the first metal electrical wire group are electrically contacted through first via holes with sixth electrical wire layer 29f of the second metal electrical wire group. All first to sixth metal electrical wire layers 29a to 29f have a vertical extension.
First and second electrical wire layers 29a and 29b of the second metal electrical wire group are electrically contacted through first via holes with first electrical wire layer 31a of the third metal electrical wire group. First metal electrical wire layer 31a has a horizontal extension. As a write global word line GWL_W second metal electrical wire layer 31b of the third metal electrical wire group is utilized. Third metal electrical wire layer 31c of the third metal electrical wire group is utilized as a read global word line GWL_R. Second metal electrical wire layer 31b and third metal electrical wire layer 31c of the third metal electrical wire group are separated from each second at a predetermined horizontal distance. Configurations shown in FIG. 3a to FIG. 3c are an original patterned configuration in which all layers between first layer and second successive layer are overlapped. However, it is difficult to be distinct from a boundary of various regions in case of the show of the overlapped configuration within FIG. 3a to FIG. 3c. Therefore, the overlapped configuration is not shown in FIG. 3a to FIG. 3c. 
FIG. 4a to FIG. 4c are patterned layout configuration diagrams for explaining process steps of other embodiment of a two-port SRAM according to a prior art invention. In other embodiment of the prior art two-port SRAM, a long axis of active regions for forming first and second load transistors TL1 and TL2 is a vertical direction.
In FIG. 4a, an N type well region 42 is formed on first part of a cell formation region 41 in order to define first and second load transistors TL1 and TL2. First and second active regions 44a and 44b is formed so that these active regions 44a and 44b are separated from each second within cell formation region 41. A vertical direction of these active regions 44a and 44b is a long axis. In second region except the N-type well region 42 in the cell formation region 41 which is a P-type well region, third and fourth active regions 44c and 44d which face each second are formed by meeting at least first extension portion to a perpendicular direction from an intersection between a long axis of a horizontal direction and a long axis of a vertical direction. Also, fifth active region 44e is formed on a separation region of first and second active regions 44a and 44b. 
Sixth and seventh active regions 44f and 44g are respectively formed on left and right lower portions of third and fourth active regions 44c and 44d. A first metal electrode layer 45a is formed in order to be utilized as gate electrodes of first load transistor TL1, first write drive transistor /WTD1, and first read drive transistor RTD1. First metal electrode layer 45a has a configuration in which a central portion of first active region 44a is passed on in a vertical direction and at least two portions of third active regions 44c are passed on. Second metal electrode layer 45b is formed so that a central portion of second active region 44b is passed on in a horizontal direction and at least two portions of fourth active regions 44d are passed on. As gate electrodes of second load transistor TL2, second write drive transistor WTD2, and second read drive transistor RTD2 functions second metal electrode layer 45b. Third metal electrode layer 45c is formed in order to be utilized as gate electrodes of first and second write access transistors WTA1 and WTA2. Fifth metal electrode layer 45d is formed in order to be utilized as gate electrodes of first and second read access transistors RTA1 and RTA2. A plurality of contact regions 46 are formed on first to seventh active regions 44a to 44g of which any portion are not passed on by first to fourth metal electrode layers 45a to 45d or on first to fourth metal electrode layers 45a to 45d. Fifth active regions 44e is formed in order to define a bias of the N-type well region 42.
In FIG. 4b, first metal electrical wire layer 47a is electrically contacted with first electrodes of first and second load transistor TL1 and TL2. A electrical connection of gate electrodes of first load transistor TL1, first write drive transistor WTD1, and read drive transistor RTD1 and first common node CN1 are made by second metal electrical wire layer 47b. Third metal electrical wire layer 47c causes second common node CN2 to make an electrical connection of gate electrodes of second load transistor TL2, second write drive transistor WTD2, and second read drive transistor RTD2. Fourth metal electrical wire layer 47d which is a horizontal extension, is formed in order to electrically contact with gate electrodes of first and second write access transistor WTA1 and WTA2. In order to electrically contact with gate electrodes of first and second read access transistors RTA1 and RTA2, fifth metal electrical wire layer 47e is formed. Sixth and seventh metal electrical wire layer 47f and 47g are formed in order to electrically contact with first electrodes of first and second write access transistors WTA1 and WTA2. Eighth and ninth metal electrical wire layers 47h and 47i are formed in order to electrically contact with first electrodes of first and second read access transistors RTA1 and RTA2. With third common node CN3 of first write drive transistor WTD1 and first read drive transistor RTD1 is electrically contacted tenth metal electrical wire layer 47j. Eleventh metal electrical wire layer 47k is formed in order to electrically contact with fourth common node CN4 of second write drive transistor WTD2 and second read drive transistor RTD2. Twelfth and thirteenth metal electrical wire layers 47l and 47m are formed in order to contact with power supply ground VSS. First plurality of via holes are respectively formed on sixth to thirteenth metal electrical wire layers 47f to 47m. First metal electrical wire layer of first metal electrical wire group has a first and second active regions 44a and 44b of which a long axis is extended to a vertical direction. Source and drain electrodes are positioned at the same layer as fifth active region 44e, thereby having a straight and vertical extension.
In FIG. 4c, first metal electrical wire layer 49a of second metal electrical wire group is formed so that its electrical wire layers 49a is contacted through first via holes with tenth and twelfth metal electrical wire layers 47j and 47l of first metal electrical wire group to a vertical direction. Second metal electrical wire layer 49b of second metal electrical wire group is formed so that its electrical wire layers 49b is contacted through first via holes with eleventh and thirteenth metal electrical wire layers 47k and 47m of first metal electrical wire group to a vertical direction. Third metal electrical wire layer 49c of second metal electrical wire group is formed so that its electrical wire layers 49c is contacted through first via holes with eighth metal electrical wire layer 47h of first metal electrical wire group to a vertical direction. Fourth metal electrical wire layer 49d of second metal electrical wire group is formed so that its electrical wire layers 49d is contacted through first via holes with ninth metal electrical wire layer 47i of first metal electrical wire group to a vertical direction. Fifth metal electrical wire layer 49e of second metal electrical wire group is formed so that its electrical wire layers 49e is contacted through first via holes with sixth metal electrical wire layer 47f of first metal electrical wire group to a vertical direction. Sixth metal electrical wire layer 49f of second metal electrical wire group is formed so that its electrical wire layers 49f is contacted through first via holes with seventh metal electrical wire layer 47g of first metal electrical wire group to a vertical direction. First metal electrical wire layer 51a of third metal electrical wire group is formed so that its electrical wire layers 51a is contacted through second via holes with first and second metal electrical wire layers 49a and 49b of second metal electrical wire group to a horizontal direction. As a write global word line GWL_W second metal electrical wire layer 51b of the third metal electrical wire group is utilized. Third metal electrical wire layer 51c of the third metal electrical wire group is utilized as a read global word line GWL_R.
In the above-described SRAM, each electrode at the load transistors included in first unit cell and in second unit cell neighbored to the corresponding first unit cell is mutually connected to power supply source line, thereby being happened at the same time at in-operation of all unit cells that are linked to power supply line VCCL. Also, common electrodes of write drive transistor and read drive transistor in every unit cell are electrically connected to power supply ground VSS, such that a problem is happened at the same time at all unit cells that are linked to power supply ground VSS.
Further, the conventional SRAM cell had the second problem that occupation region of a load transistor for obtaining a loading effect is narrow in its width because the width of the load transistor is extended to a vertical direction, resulting in degrading its trust and decreasing its operation speed.